mipsfpga

I am really excited with today’s announcement. You may know that, a couple of months back, Imagination Technologies presented the Imagination University Programme (IUP) and, as a part of it, the MIPSfpga programme, where academicals around the globe will have free, unlimited access to a MIPS microAptiv CPU RTL code as well as a complete repertoire of tools and teaching materials.

As part of this programme, Imagination will be hosting several one-day workshops in Europe where attenders will learn how to set up, use, and modify and extend the microAptiv core, loading it into a Xilinx FPGA and programming code to run on it. The workshops will cover the following:

  • Welcome & Introduction to the Imagination University Programme (“IUP”)
  • Introduction to MIPSfpga
  • MIPSfpga and Vivado Demonstration:
    1. Simulation: Increment LEDs program
    2. Increment LEDs delay program on the Nexys 4 DDR
    3. Synthesizing core on the Nexys4 DDR
    4. Codescape MIPS SDK: using Codescape to develop & debug C and assembly code
      Bus Blaster/OpenOCD: using the Bus Blaster JTAG probe and OpenOCD to debug a target system
  • Lab 1: Writing C code
  • Lab 2: Adding a 7-segment display I/O
  • Integrating Xilinx IP blocks with MIPSfpga
  • Porting to other boards – Example: Digilent’s Basys3
  • Teaching Materials for MIPSfpga / Wrap-up / Q&A

Three workshops will take place between September and December in London, Darmstadt, and Madrid.

So the obvious question here is: What am I so excited about?

Well, I’m glad to announce that I will be one of the MIPSfpga trainers in the Madrid workshop, which will take place at the Universidad Computense de Madrid on December 9th & 10th 2015. It trhilling, scary, and awesome, all at once!

You can find more information about it on the MIPSfpga Workshops in Europe 2015 flyer, and the registration for all of the workshops is already open for applications.

See you in December in Madrid!

MIPSfpga in Madrid: Save the date!
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