esedano

Senior CPU Design Engineer
ARM Holdings
Cambridge, Cambridgeshire
CB1 9NJ
United Kingdom

Employment

Jul. 2017 – Nowadays.
Senior CPU Design Engineer, ARM.

Jul. 2016 – Jul. 2017.
Leading Hardware Design Engineer, Imagination Technologies, MIPS Processor IP.

Dec. 2013 – Jun. 2016.
Hardware Design Engineer, Imagination Technologies, MIPS Processor IP.
– Lead designer in charge of the Instruction Fetch Unit of next-generation multi-threaded MIPS processor (I6400). Responsible for design, implementation and verification of the unit, ensuring that it met the standards of quality, performance and power consumption.
– Responsible for a team of 3 people working on the Instruction Fetch Unit, ensuring that team worked efficiently and meeting deadlines. Responsible of supervising young engineer placement (3 months) and university professor sabbatical (6 months).
– Design of verification framework for unit level testing (Verilog, SystemVerilog, UVM) and constrain-randomised programs for core-level verification (Perl, MIPS ASM).
– Design of a custom scripted framework for regression management similar to ExecMan or vManager (Python).
– Involvement in the University Programme as developer and trainer (MIPSfpga programme).

Jul. 2006 – Aug. 2008.
Teacher, Intecysa School (Aramaia S.L.).
Over the span of two years, I taught Automaton Theory and Finite Languages to more than a dozen student groups in both semester-long and summer-intensive courses.

Education

2010 – 2016.
Ph.D., Electronic Engineering. Univ. Politécnica de Madrid. Automated wordlength optimization framework for multi-source statistical interval-based analysis of nonlinear systems with control-flow structures

2008 – 2010.
Master’s Degree, Research in Computer Engineering. Univ. Complutense de Madrid. Tecnicas de simplificación de la política de reemplazamiento cache Probabilistic Escape LIFO

2002 – 2008.
Bachelor’s Degree, Computer Engineering. Univ. Complutense de Madrid. Implementación de una plataforma HW para la evaluación de predictores e saltos sobre arquitectura SPARC v8

Publications & patents

See Publications section.

Lifelong learning

See Lifelong learning section.

Academical experience

Doctoral Scholarship, work on high-precision FPGA-based noise reduction techniques for infrared interferometers fusion diagnostics. International Programme for Attracting Talent, Campus of International Excellence, Universidad Politécnica de Madrid. January, 2011 – December 2013.

Department internship, work on wordlength optimization techniques and noise quantization for DSP platforms. DIE department, Universidad Politéecnica de Madrid. September, 2010 – December, 2011.

Department internship, work on thermal-aware compiler techniques. DACyA department, Universidad Complutense de Madrid / Ecole Polytechnique Fédérale de Lausanne. September, 2008 – September, 2009.

Department internship, work on branch prediction schemes on FPGA platforms. DACyA department, Universidad Complutense de Madrid. October, 2007 – June, 2008.

Research stays

Sept. 2012 – Dec. 2012.
IETR-INSA (Rennes, France) with Prof. Daniel Menard.

Nov. 2008 – Apr. 2009.
ESL-EPFL (Lausanne, Switzerland) with Prof. David Atienza.

Honors

  • Honourific collaborator of DACyA (Automation and Computer Architecture Department) at UCM (2016/17, 2017/18)
  • Ph.D. Thesis awarded with cum laude calification.
  • Degree Project passed with distinction.
  • Degree Project awarded with Second Place in I Edition of Premios Fin de Carrera Sun Microsystems (Bachelor Project Prizes Sun Microsystems).
  • Paper “Implementation of a hardware branch-predictor evaluation platform based on FPGAs” awarded with Gold Leaf Certificate for being among the first decile in reviewing scores.

Technical skills

Programming languages (skill)

Verilog (High), VHDL (High), Python (High), Java (Intermediate), C/C++ (Intermediate), MySQL (Intermediate), Prolog (Beginner), Haskell (Beginner), Handel-C (Beginner), Perl (Beginner).

Languages

Spanish, mother tongue.
English, C1 level. CAE Certification.
French, A2 level.

Professional affiliations

  • European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC)

Additional information

Reviewer for The Computer Journal, ISSN 1460-2067 (online), 0010-4620 (print), Oxford University Press (2014).
Reviewer for ReConFig 2013 (Reconfigurable Computing and FPGAs, International Conference on).
Designated Reviewer for ISIEA 2013 (Industrial Electronics & Applications, IEEE Symposium on).
Designated Reviewer for ISIEA 2012 (Industrial Electronics & Applications, IEEE Symposium on).
Reviewer for DASIP 2012 (Design & Architectures for Signal & Image Processing, Conference on).
Reviewer for EURASIP Journal of Embedded Systems, ISSN 1687-3955, Hindawi Publishing (2010).
Reviewer for SPL 2010 (Programmable Logic, VII Southern Conference on).